1. Field of the Invention
The present invention relates to a semiconductor device, and, more particularly relates to a semiconductor device including a delay control circuit that generates an operation timing signal by delaying a reference signal.
2. Description of Related Art
An internal circuit of a semiconductor device generally uses a clock signal to determine its operation timing. Therefore, it suffices to increase a frequency of the clock signal to operate the semiconductor device at high speed.
However, in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), increasing a frequency of a clock signal cannot always lead to a high speed operation of its memory cell array because the memory cell array performs an analog operation. Consequently, an interval from a timing for starting a predetermined operation (for example, an activation timing of a word driver) for the memory cell array to another timing for starting a subsequent operation (for example, an activation timing of a sense amplifier) is virtually constant regardless of the frequency of the clock signal. In such an analog operation unit, a delay control circuit is employed for generating a timing signal.
The delay control circuit is a circuit including a plurality of delay elements connected in series. A pulse signal used as a reference signal is input to the delay control circuit, and an operation timing signal is output therefrom. In the example described above, a pulse signal synchronized with the activation timing of the word driver is input to the delay control circuit, and an activation timing signal for a sense amplifier is output from the delay control circuit.
However, a delay amount of each of the delay elements is not always constant, and varies according to various conditions. Major factors that cause a variation of the delay amount include: first, a deviation of threshold voltage caused by a process fluctuation (P variation); second, a variation in power source voltage (V variation); and third, a variation in ambient temperature (T variation). The variation caused by these factors is called “PVT variation”. The larger the PVT variation is, the more the operation timing is deviated from its design value, which causes a malfunction of a device in some cases.
When a delay amount of a delay control circuit is decreased by a large amount from its design value due to the PVT variation, an operation timing signal, which is an output of the delay control circuit, becomes activated earlier than a timing at which the operation timing signal is supposed to be activated. If the operation timing signal is an activation signal of a sense amplifier, for example, a sense amplifier becomes activated before a sufficient potential difference is generated between bit lines, resulting in an erroneous read operation. To prevent such a malfunction, it is necessary to set the delay amount of the delay control circuit with a sufficiently large design margin, such that the operation timing signal is not activated too early even when the delay amount of the delay control circuit is minimized due to the PVT variation. However, in this case, the performance can be degraded because the activation of the operation timing signal becomes unnecessarily slow under a normal operation condition.
Meanwhile, Japanese Patent Application Laid-open No. 2005-267744 (hereinafter, “Patent Document 1”) proposes a method to cope with the problem, in which an activation timing of a sense amplifier is generated by using a dummy word line, a dummy bit line, and a dummy cell, instead of using a plurality of delay elements.
However, in Patent Document 1, because additional circuits such as the dummy word line, the dummy bit line, and the dummy cell are required to generate a timing signal, there is a problem that the circuit size is considerably increased. In addition, with the method proposed in Patent Document 1, there is another problem that the power consumption is considerably increased because it is required to operate a dummy circuit every time an access is requested.